Current Limited Power Converter Circuits And Methods

ABSTRACT

A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. A hysteretic comparison circuit compares the current in the power train circuit to positive and negative current limits. The hysteretic comparison circuit causes a positive current in the power train circuit to decrease in a positive current limit mode in response to the positive current in the power train circuit reaching the positive current limit. The hysteretic comparison circuit causes a negative current in the power train circuit to decrease in a negative current limit mode in response to the negative current in the power train circuit reaching the negative current limit. The hysteretic comparison circuit prevents a pulse width modulation controller from controlling the power train circuit during the positive and negative current limit modes.

FIELD OF THE DISCLOSURE

The present disclosure relates to electronic circuits, and moreparticularly, to power converter circuits and methods with currentlimiting.

BACKGROUND

A power converter is a circuit that converts an input voltage into anoutput voltage. A power converter may generate a regulated outputvoltage at an output node that is coupled to a load. A power converterprovides output current to the load at the regulated output voltage, andthe load draws current from the power converter. A power converter mayhave a controller that manages the operation of the power converter bycontrolling the conduction periods of switching transistors therein.Typically, the controller measures the output voltage and based on theoutput voltage modifies duty cycles of the switching transistors. Theduty cycle of each of the switching transistors is a ratio representedby a conduction period of that transistor to a switching period of thattransistor.

BRIEF SUMMARY

According to some embodiments, a power converter circuit includes acurrent sensor circuit and a hysteretic comparison circuit. The currentsensor circuit generates an indication of a current in a power traincircuit. The power converter circuit regulates an output voltage at anoutput node of the power train circuit. The power converter circuit alsocontrols the current in the power train circuit. The hystereticcomparison circuit compares the indication of the current in the powertrain circuit to a current limit. The power converter circuit decreasesa magnitude of the current in the power train circuit in response to anindication generated by the hysteretic comparison circuit that thecurrent in the power train circuit has reached the current limit.

According to some embodiments, the hysteretic comparison circuitcompares the current in the power train circuit to a positive currentlimit and to a negative current limit. The hysteretic comparison circuitcauses a positive current in the power train circuit to decrease in apositive current limit mode in response to the positive current in thepower train circuit reaching the positive current limit. The hystereticcomparison circuit causes a negative current in the power train circuitto decrease in a negative current limit mode in response to the negativecurrent in the power train circuit reaching the negative current limit.

Various objects, features, and advantages of the present invention willbecome apparent upon consideration of the following detailed descriptionand the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a power converter circuit having a current limitcircuit that monitors positive and negative output currents, accordingto an embodiment.

FIG. 2A illustrates an example of a current sensor circuit that includesan integrated current replicator circuit, according to an embodiment.

FIGS. 2B-2C illustrate an example of a current sensor circuit having tworesistors, two transistors, and two operational amplifiers, according toanother embodiment.

FIG. 3 illustrates an example of the hysteretic comparison circuit ofFIG. 1, according to an embodiment.

FIG. 4A is a timing diagram that illustrates an example of the currentthrough the power train circuit as the power converter circuit of FIG. 1enters and exits a positive current limit mode of operation, accordingto an embodiment.

FIG. 4B is a timing diagram that illustrates an example of the currentthrough the power train circuit as the power converter circuit of FIG. 1enters and exits a negative current limit mode of operation, accordingto an embodiment.

FIG. 5 is a flow chart showing operations that may be performed todetermine when the power converter circuit of FIG. 1 enters and exitsthe positive current limit mode, according to an embodiment.

FIG. 6 is a flow chart showing operations that may be performed todetermine when the power converter circuit of FIG. 1 enters and exitsthe negative current limit mode, according to an embodiment.

DETAILED DESCRIPTION

As discussed above, a power converter provides output current to a loadat a regulated output voltage using switches, such as switchingtransistors. A power converter may also have an output filter thatincludes an inductor and a capacitor. In response to the current drawnby the load from a power converter increasing, the power converterincreases the output current provided to the load to maintain the outputvoltage at a substantially constant voltage. If the current drawn by theload increases substantially in a short time period, the power convertermay cause the output current to increase to the maximum output currentof the power converter. Power converters may have maximum allowedpositive output currents and atypically maximum allowed negative outputcurrents. The maximum positive and negative output currents may beselected, for example, to prevent the inductor from saturating.

A power converter typically has a current limit circuit that turns offthe main switching transistor if the peak or the average positive outputcurrent in the power train of the power converter reaches the maximumpositive output current. However, previously known current limitcircuits do not always prevent the output current of a power converterfrom exceeding its maximum positive output current for a few reasons.First, previously known current limit circuits are often slow to respondto the output current of the power converter reaching the maximumpositive output current. The delay in responding to the output currentreaching the maximum positive output current may allow the outputcurrent to substantially exceed the maximum positive output current.Also, previously known current limit circuits do not maintain the mainswitching transistor off for long enough to prevent the output currentfrom reaching the maximum positive output current again very soon afterthe main switching transistor is turned back on. If the load currentremains high, the output current of the power converter may repeatedlyreach and exceed the maximum positive output current. In addition,previously known current limit circuits do not measure a negativecurrent in the power train of a power converter. A negative current inthe power train of a power converter may, for example, refer to acurrent flowing through the inductor toward the switching transistorsaway from the load, instead of toward the load. A negative current inthe power train flows away from an output node of the power train. Anegative current in the power train of a power converter may exceed amaximum negative output current of the power converter, which can alsocause the inductor to saturate. A positive current in the power trainflows toward the output node of the power train and toward the load.

According to some embodiments disclosed herein, a power convertercircuit has a current limit circuit that includes a current sensorcircuit and a hysteretic comparison circuit. The current sensor circuitcontinuously monitors the output current of the power converter circuitin a power train. The current sensor circuit measures positive andnegative output currents of the power converter circuit to generate anindication of the output current in a current sense signal. The currentsense signal is provided to the hysteretic comparison circuit. Thehysteretic comparison circuit compares the current sense signal to apositive current limit. If the output current reaches the positivecurrent limit, the power converter maintains the main switchingtransistor off during a positive current limit mode, until the outputcurrent reaches a minimum positive current of the positive current limitmode. Thus, the hysteretic comparison circuit limits the magnitude ofthe output current when the output current is flowing toward the outputnode of the power train. The hysteretic comparison circuit also comparesthe current sense signal to a negative current limit. If the outputcurrent reaches the negative current limit, the power convertermaintains the auxiliary switching transistor off during a negativecurrent limit mode, until the output current reaches a minimum negativecurrent of the negative current limit mode. Thus, the hystereticcomparison circuit limits the magnitude of the output current when theoutput current is flowing away from the output node of the power train.During the current limit modes, the conductive states of the switchingtransistors are controlled by the current limit circuit, and the currentlimit circuit prevents a controller from controlling the switchingtransistors using pulse width modulation.

FIG. 1 illustrates a power converter circuit 100 according to anembodiment. Power converter circuit 100 includes power train circuit101, driver circuit 102, gate circuit 103, controller circuit 104,current sensor circuit 105, and hysteretic comparison circuit 106. Powertrain circuit 101 includes a main switching transistor 111, an auxiliaryswitching transistor 112, an inductor 114, and an output capacitor 116.Main switching transistor 111 may be, for example, a P-channel fieldeffect transistor (FET), and auxiliary switching transistor 112 may be,for example, an N-channel FET. Transistors 111 and 112 may be, forexample, power metal oxide semiconductor field-effect transistors (i.e.,power MOSFETs). Transistors 111 and 112 act as switches. Therefore, anysemiconductor circuits that function as switches may be used astransistors 111-112. Power converter circuit 100 may also be referred toas a switching voltage regulator circuit or a DC/DC converter circuit.In some embodiments, switching transistors 111-112, driver circuit 102,gate circuit 103, current sensor circuit 105, and hysteretic comparisoncircuit 106 are all in one integrated circuit (IC), and controllercircuit 104 is in a separate integrated circuit. In some embodiments,one or more of the circuits in power train circuit 101, such as inductor114 and capacitor 116, are discrete components.

Power train circuit 101 receives an input voltage V_(IN) at an inputfrom a source of electrical power and generates a regulated outputvoltage V_(OUT) at an output node based on the input voltage V_(IN).Power converter 100 converts the input voltage V_(IN) into the outputvoltage V_(OUT). Power train circuit 101 shown in FIG. 1 employs astep-down (buck) converter topology that converts an input voltageV_(IN) into an output voltage V_(OUT) that is less than the inputvoltage V_(IN). Thus, V_(IN) in FIG. 1 is greater than V_(OUT). Althoughpower train circuit 101 is a step-down converter, embodiments of thepresent invention may be included in other power converter topologies,such as in a step-up (boost) power converter circuit that converts aninput voltage into an output voltage that is greater than the inputvoltage.

The output voltage V_(OUT) of power converter circuit 100 is provided toa load that is coupled to the output node of power converter circuit100. The load may be, for example, a microprocessor integrated circuit,a field programmable gate array integrated circuit, or any other type ofcircuit or system that draws current. Power converter circuit 100provides output current to the load at V_(OUT), and the load drawscurrent from power converter circuit 100. Power converter circuit 100alternately turns the switching transistors 111-112 on and off toprovide output current to the load and to maintain the output voltageV_(OUT) at a substantially constant voltage. The output capacitor 116 iscoupled between the output node of power converter circuit 100 and aground node that is at a ground voltage. Output capacitor 116 filtersV_(OUT) to help maintain V_(OUT) at a substantially constant DC voltage.

Driver circuit 102 generates two drive voltages DRV1 and DRV2 that areprovided to the gates of transistors 111 and 112, respectively. Drivercircuit 102 controls the conductive states of the switching transistors111 and 112 by controlling the drive voltages DRV1 and DRV2,respectively. Driver circuit 102 switches transistors 111 and 112 out ofphase, such that when one of transistors 111-112 is on, the other one oftransistors 111-112 is off. Power converter circuit 100 preventstransistors 111 and 112 from being on at the same time. During eachswitching period of transistors 111-112, transistor 111 is on andtransistor 112 is off for a primary portion of the switching period, andtransistor 111 is off and transistor 112 is on for a complementaryportion of the switching period. The on-times of switching transistors111 and 112 may be separated by small time intervals in each switchingperiod during which both of transistors 111-112 are off to avoidcross-conduction there between.

During the primary portion of each switching period of transistors111-112, driver circuit 102 maintains transistor 112 off, and drivercircuit 102 maintains transistor 111 on, causing the input voltageV_(IN) to be coupled to output inductor 114 through transistor 111.During the primary portion of each switching period, the current ILflowing through inductor 114 increases in response to current flowingthrough transistor 111 between input voltage V_(IN) and inductor 114.

During the complementary portion of each switching period of transistors111-112, driver circuit 102 maintains transistor 111 off, and drivercircuit 102 maintains transistor 112 on, causing the inductor 114 to becoupled to a ground node at the source of transistor 112 that is at theground voltage. When auxiliary transistor 112 is on, transistor 112provides a circuit path to maintain the continuity of the inductorcurrent IL flowing through the inductor 114. During the complementaryportion of each switching period, the current IL flowing throughinductor 114 decreases in response to current flowing through transistor112 between the ground node and inductor 114.

The controller circuit 104 generates one or more PWM signals to controlthe duty cycles of the switching transistors 111-112 using drivercircuit 102. Controller circuit 104 may be referred to as a pulse-widthmodulation (PWM) controller circuit. The one or more PWM signalsgenerated by controller circuit 104 are provided to one or more inputsof gate circuit 103. Gate circuit 103 may be, for example, a logic gatecircuit, such as an AND or a NAND logic gate circuit. Hystereticcomparison circuit 106 generates a control signal CNTL that is providedto an additional input of gate circuit 103. Gate circuit 103 generatessignals PWMDR at its outputs.

Power converter circuit 100 operates in at least three modes ofoperation that are referred to as a pulse width modulation (PWM) mode, apositive current limit mode, and a negative current limit mode. Thecurrent limit modes are described in detail below. During the pulsewidth modulation mode, hysteretic comparison circuit 106 causes thecontrol signal CNTL to have a value that causes gate circuit 103 to passthe values of the PWM signals to the outputs of gate circuit 103 insignals PWMDR. For example, if gate circuit 103 is an AND gate or a NANDgate, hysteretic comparison circuit 106 drives control signal CNTL to alogic high state during pulse width modulation mode, causing gatecircuit 103 to drive signals PWMDR to the same values as signals PWM.

Signals PWMDR are provided to inputs of driver circuit 102. Drivercircuit 102 generates the drive voltages DRV1 and DRV2 based on thePWMDR signals during PWM mode. In response to first values in the PWMDRsignals, driver circuit 102 turns on transistor 111 and turns offtransistor 112. In response to second values in the PWMDR signals,driver circuit 102 turns off transistor 111 and turns on transistor 112.Controller circuit 104 causes the PWM and PWMDR signals to alternatebetween the first and second values during PWM mode.

Controller circuit 104 receives the input voltage V_(IN) and the outputvoltage V_(OUT) at inputs. Controller circuit 104 generates the PWMsignals in response to the input voltage V_(IN) and in response to theoutput voltage V_(OUT). During the pulse width modulation mode,controller circuit 104 varies the PWM and the PWMDR signals to vary theduty cycles of the switching transistors 111-112 in order to regulatethe output voltage V_(OUT) and to maintain the output voltage V_(OUT) ata substantially constant voltage.

For example, controller circuit 104 may include a comparator circuitthat compares the output voltage V_(OUT) (or a divided down version ofV_(OUT)) to a reference voltage. In response to V_(OUT) decreasing belowa target voltage for V_(OUT) that is indicated by the reference voltage,controller circuit 104 adjusts the PWM and PWMDR signals to cause drivercircuit 102 to maintain transistor 111 on and transistor 112 off for alonger period of time during each switching period of transistors111-112. Thus, controller circuit 104 and driver circuit 102 increasethe duty cycle of transistor 111 and decrease the duty cycle oftransistor 112 in response to V_(OUT) decreasing below the targetvoltage, causing the current IL in inductor 114 to increase and causingV_(OUT) to increase to the target voltage.

In response to V_(OUT) increasing above the target voltage for V_(OUT),controller circuit 104 adjusts the PWM and PWMDR signals to cause drivercircuit 102 to maintain transistor 112 on and transistor 111 off for alonger period of time during each switching period of transistors111-112. Thus, controller circuit 104 and driver circuit 102 decreasethe duty cycle of transistor 111 and increase the duty cycle oftransistor 112 in response to V_(OUT) increasing above the targetvoltage, causing the current IL in inductor 114 to decrease and causingV_(OUT) to decrease to the target voltage. Controller circuit 104 anddriver circuit 102 maintain the duty cycles of transistors 111-112constant in response to V_(OUT) being at the target voltage. Controllercircuit 104 and driver circuit 102 may also vary the duty cycles ofswitching transistors 111-112 in response to changes in the inputvoltage V_(IN) during the pulse width modulation mode.

Current sensor circuit 105 senses a current IPT in power train circuit101. Current sensor circuit 105 generates a current sense signal CSbased on the current IPT. Current sensor circuit 105 causes the currentsense signal CS to be indicative of the current IPT in power traincircuit 101. Current sensor circuit 105 continuously monitors thecurrent IPT in power train circuit 101 during each on-time of switchingtransistor 111 and during each on-time of switching transistor 112.

Current sensor circuit 105 may be in the same integrated circuit (IC)with transistors 111-112, or current sensor circuit 105 may be in aseparate IC. Current sensor circuit 105 can measure a positive currentor a negative current in power train circuit 101. A positive current inpower train circuit 101 may refer to the inductor current IL flowingfrom node N1 to V_(OUT), as shown by the direction of the arrow inFIG. 1. A negative current in power train circuit 101 may refer to theinductor current IL flowing in the opposite direction as a positivecurrent.

FIGS. 2A-2C illustrate some examples of current sensor circuit 105,according to various embodiments. FIG. 2A illustrates an example ofcurrent sensor circuit 105 that includes an integrated currentreplicator circuit 200, according to an embodiment. The integratedcurrent replicator circuit 200 includes two current sense resistors201-202 having known resistances, two transconductance amplifiers (notshown), and additional circuitry (not shown). Resistor 201 is coupledbetween the input voltage V_(IN) and the source of switching transistor111. When transistor 111 is on, current flows through resistor 201 andtransistor 111, generating a first voltage V1 across resistor 201, asshown in FIG. 2A. Voltage V1 and the resistance of resistor 201 indicatethe current through resistor 201 and transistor 111 when transistor 111is on. The first transconductance amplifier generates a first currentsignal indicative of the voltage V1 across resistor 201.

Resistor 202 is coupled between the source of switching transistor 112and the ground node. When transistor 112 is on, current flows throughtransistor 112 and resistor 202, generating a second voltage V2 acrossresistor 202, as shown in FIG. 2A. Voltage V2 and the resistance ofresistor 202 indicate the current through resistor 202 and transistor112 when transistor 112 is on. The second transconductance amplifiergenerates a second current signal indicative of the voltage V2 acrossresistor 202. Integrated current replicator circuit 200 includes anadditional amplifier circuit that generates the current sense signal CSbased on the first and second current signals generated by thetransconductance amplifiers. Further details of an integrated currentreplicator, such as integrated current replicator circuit 200 aredisclosed in commonly-assigned U.S. patent application 20150280558,filed Mar. 27, 2014, which is incorporated by reference herein in itsentirety.

Integrated current replicator circuit 200 can measure a positive currentor a negative current through either of resistors 201 or 202. Integratedcurrent replicator circuit 200 can measure a positive current flowingthrough resistor 201 from V_(IN) to transistor 111 or a negative currentflowing through resistor 201 from transistor 111 to V_(IN). Integratedcurrent replicator circuit 200 can also measure a positive currentflowing through resistor 202 from the ground node to transistor 112 or anegative current flowing through resistor 202 from transistor 112 to theground node.

FIGS. 2B-2C illustrate another example of current sensor circuit 105that includes two resistors, two transistors, and operationalamplifiers, according to another embodiment. FIG. 2B illustrates a senseresistor 210, a P-channel FET 211, and an operational amplifier (op amp)circuit 215. Resistor 210 and transistor 211 are coupled in parallelwith switching transistor 111. The gate of transistor 211 is coupled toreceive the same drive signal DRV1 from driver circuit 102 that isprovided to the gate of transistor 111. Thus, driver circuit 102 turnstransistors 111 and 211 on concurrently during each switching period.When transistors 111 and 211 are on, a current flows through senseresistor 210 and transistor 211 that is a fraction of the currentflowing through the main switching transistor 111. The voltage V1 acrossresistor 210 is proportional to the current through resistor 210.Voltage V1 is provided to inputs of operational amplifier circuit 215.The op amp circuit 215 causes the current sense signal CS to indicatethe current through transistor 111 while transistor 111 is on.

FIG. 2C illustrates a sense resistor 220, an N-channel FET 212, and anoperational amplifier (op amp) circuit 217. Resistor 220 and transistor212 are coupled in parallel with switching transistor 112. The gate oftransistor 212 is coupled to receive the same drive signal DRV2 fromdriver circuit 102 that is provided to the gate of transistor 112. Thus,driver circuit 102 turns transistors 112 and 212 on concurrently duringeach switching period. When transistors 112 and 212 are on, a currentflows through sense resistor 220 and transistor 212 that is a fractionof the current flowing through switching transistor 112. The voltage V2across resistor 220 is proportional to the current through resistor 220.Voltage V2 is provided to inputs of operational amplifier circuit 217.Op amp circuit 217 causes the current sense signal CS to indicate thecurrent through transistor 112 while transistor 112 is on.

The current sensor circuit of FIGS. 2B-2C can measure a positive currentor a negative current through either one of resistors 210 or 220. Op amp215 can measure a positive current flowing through resistor 210 fromV_(IN) to node N1 or a negative current flowing through resistor 210from node N1 to V_(IN). Op amp 217 can measure a positive currentflowing through resistor 220 from the ground node to node N1 or anegative current flowing through resistor 220 from node N1 to the groundnode.

According to another embodiment, current sensor circuit 105 includes twocurrent transformers. One of the current transformers is coupled inseries with switching transistor 111, and the other current transformeris coupled in series with switching transistor 112. The outputs of thetwo current transformers are summed in order to obtain the DC current inpower train circuit 101. The current transformers can measure a positivecurrent or a negative current in power train circuit 101.

According to yet another embodiment, current sensor circuit 105 includescircuitry that uses direct-current resistance (DCR) current sensing. Inthis embodiment, current sensor circuit 105 includes a seriesresistor-capacitor (RC) network that is coupled in parallel withinductor 114. The RC network uses DCR current sensing to measure thecurrent through inductor 114 by measuring the resistance of inductor114. The resistor and the capacitor in the RC network of current sensorcircuit 105 are selected to cause the RC time constant of the RC networkto be equal to an L/R_(L) time constant of inductor 114, where L is theinductance of inductor 114, and R_(L) is the DC resistance of inductor114. This embodiment can also be used to measure a positive current or anegative current in power train circuit 101.

Referring again to FIG. 1, power converter circuit 100 has a feedbackloop circuit that includes current sensor circuit 105, hystereticcomparison circuit 106, and driver circuit 102. The current sensorcircuit 105 and the hysteretic comparison circuit 106 are a currentlimit circuit that prevents the current in power train circuit 101 fromexceeding a positive current limit. The current limit circuit alsoprevents a negative current in power train circuit 101 from exceeding anegative current limit. Further details of the current limit circuit arenow described.

As shown in FIG. 1, the current sense signal CS generated by currentsensor circuit 105 is provided to an input of hysteretic comparisoncircuit 106. Hysteretic comparison circuit 106 generates control signalCNTL and hysteretic drive signals HYSDR based on the current sensesignal CS. The hysteretic drive signals HYSDR are provided to drivercircuit 102.

FIG. 3 illustrates an example of hysteretic comparison circuit 106,according to an embodiment. In the exemplary embodiment of FIG. 3,hysteretic comparison circuit 106 includes a first hysteretic comparatorcircuit 301, a second hysteretic comparator circuit 302, and a NOR gatecircuit 303. Also, in the embodiment of FIG. 3, the current sense signalCS is a voltage signal. The current sense signal CS is provided to thenon-inverting input of hysteretic comparator circuit 301. A firstreference voltage VREFA is provided to the inverting input of hystereticcomparator circuit 301. Hysteretic comparator circuit 301 generates afirst hysteretic drive signal HYSDR1 at its output that is based on thedifference between the voltage of signal CS and reference voltage VREFA.The current sense signal CS is also provided to the inverting input ofhysteretic comparator circuit 302. A second reference voltage VREFB isprovided to the non-inverting input of hysteretic comparator circuit302. Hysteretic comparator circuit 302 generates a second hystereticdrive signal HYSDR2 at its output that is based on the differencebetween reference voltage VREFB and the voltage of signal CS. Hystereticdrive signals HYSDR1 and HYSDR2 are collectively referred to ashysteretic drive signals HYSDR in FIG. 1.

A hysteretic comparator, such as hysteretic comparator circuits 301 and302, has two thresholds. A hysteretic comparator determines which of itstwo thresholds to apply to the input voltage of the hystereticcomparator based on the current state (high or low) of the outputvoltage of the hysteretic comparator. Each of the hysteretic comparatorcircuits 301-302 may include, for example, a comparator or amplifiercircuit coupled to a positive feedback loop circuit. The positivefeedback loop circuit causes the hysteretic comparator to be responsiveto the state of its output voltage in order to determine which of itstwo thresholds to compare to its input voltage.

Hysteretic comparator circuit 301 has a first threshold VTPU and asecond threshold VTPL. The first threshold VTPU and the second thresholdVTPL represent two different voltage thresholds. The difference betweenVTPU and VTPL equals the hysteresis of comparator circuit 301. The firstthreshold VTPU is indicative of a positive current limit ITPU for thecurrent through power train circuit 101. In response to the currentthrough power train circuit 101 reaching the positive current limitITPU, power converter circuit 100 enters the positive current limitmode. The second threshold VTPL is indicative of a positive minimumcurrent ITPL of the positive current limit mode. In response to thecurrent through power train circuit 101 reaching the positive minimumcurrent ITPL, power converter circuit 100 exits the positive currentlimit mode and returns to pulse width modulation mode. The firstthreshold VTPU and the second threshold VTPL of hysteretic comparatorcircuit 301 are determined by the reference voltage VREFA and othercharacteristics of comparator circuit 301. The reference voltage VREFAmay be programmably adjustable by a user or by other circuitry to varythe thresholds of hysteretic comparator circuit 301.

Further details of how power converter circuit 100 enters and exits thepositive current limit mode are now described. During the normaloperation of hysteretic comparison circuit 106, hysteretic comparatorcircuit 301 monitors the current sense signal CS to determine when apositive current through power train circuit 101 increases to equal orexceed the positive current limit ITPU. The current sense signal CSrising to the first threshold VTPU of hysteretic comparator circuit 301indicates that the current through power train circuit 101 has increasedto the positive current limit ITPU. In response to the current sensesignal CS increasing to the first threshold VTPU of hystereticcomparator circuit 301, hysteretic comparator circuit 301 asserts thedrive signal HYSDR1 to a logic high state, causing NOR gate circuit 303to de-assert the CNTL signal to a logic low state, and causing powerconverter 100 to enter the positive current limit mode. In response tosignal CNTL being in a logic low state, gate circuit 103 prevents thevalues of the PWM signals from propagating to the PWMDR signals. Thus,hysteretic comparison circuit 106 prevents the PWM signals fromcontrolling the conductive states of switching transistors 111-112during the positive current limit mode.

In response to receiving a logic high state in the drive signal HYSDR1,driver circuit 102 turns transistor 111 off if transistor 111 is on andturns transistor 112 on if transistor 112 is off. Driver circuit 102maintains the main switching transistor 111 off and maintains theauxiliary switching transistor 112 on during the positive current limitmode in response to the logic high state in drive signal HYSDR1. As aresult of transistor 111 being off and transistor 112 being on, thecurrent IL through the inductor 114 decreases. By causing the inductorcurrent IL to decrease in the positive current limit mode, the currentlimit circuit prevents the current through power train circuit 101 fromsubstantially exceeding the positive current limit ITPU. Although insome embodiments, delay in the current limit circuit may allow thecurrent through power train circuit 101 to briefly exceed the positivecurrent limit ITPU.

During the positive current limit mode of power converter 100,hysteretic comparator circuit 301 monitors the current sense signal CSto determine when the current through power train circuit 101 hasdecreased to be equal to or less than the positive minimum current ITPLof the positive current limit mode. The current sense signal CS fallingto the second threshold VTPL of hysteretic comparator circuit 301indicates that the current through power train circuit 101 has decreasedto the positive minimum current ITPL of the positive current limit mode.In response to the current sense signal CS decreasing to the secondthreshold VTPL of hysteretic comparator circuit 301, hystereticcomparator circuit 301 de-asserts the drive signal HYSDR1 to a logic lowstate, causing NOR gate circuit 303 to assert the CNTL signal to a logichigh state, and causing power converter 100 to re-enter the pulse widthmodulation mode. When power converter circuit 100 is in the positivecurrent limit mode, the output signal HYSDR2 of hysteretic comparatorcircuit 302 is in a logic low state, and therefore, the output signalCNTL of NOR gate circuit 303 is controlled by comparator circuit 301.

In response to the CNTL signal being in a logic high state, gate circuit103 passes the values of the PWM signals to signals PWMDR. In responseto driver circuit 102 receiving a logic low state in drive signalHYSDR1, driver circuit 102 controls the conductive states of transistors111 and 112 based on the PWMDR signals, which equal the values of thecorresponding PWM signals. Controller circuit 104 then controls theconductive states of transistors 111-112 again using the PWM signals inpulse width modulation mode. Controller circuit 104 and driver circuit102 control the current IL through inductor 114 in response to thecurrent drawn by the load as indicated by the output voltage V_(OUT)during pulse width modulation mode as described above.

FIG. 4A is a timing diagram that illustrates an example of the currentthrough power train circuit 101 as power converter circuit 100 entersand exits the positive current limit mode, according to an embodiment.In the example of FIG. 4A, the current through the power train circuit101 (shown on the y axis) increases until the current reaches thepositive current limit ITPU. In response to the current through thepower train 101 reaching ITPU, power converter circuit 100 enters thepositive current limit mode, and the current through the power train 101decreases as described above. The current through power train 101 thendecreases to the positive minimum current ITPL. In response to thecurrent through power train 101 reaching ITPL, power converter circuit100 enters the pulse width modulation mode again. The current throughpower train 101 may increase or decrease in pulse width modulation modedepending on the current drawn by the load. In the example of FIG. 4A,the current drawn by the load is greater than the positive current limitITPU. Therefore, power converter circuit 100 increases the currentthrough power train 101 during each pulse width modulation mode untilthe positive current limit ITPU is reached.

Referring again to FIG. 3, hysteretic comparator circuit 302 has a firstthreshold VTNU and a second threshold VTNL. The first threshold VTNU andthe second threshold VTNL represent two different voltage thresholds.The difference between VTNU and VTNL equals the hysteresis of comparatorcircuit 302. The first threshold VTNU is indicative of a negativecurrent limit −ITNU (i.e., a maximum negative current) for the currentthrough power train circuit 101. In response to the current throughpower train circuit 101 reaching the negative current limit −ITNU, powerconverter circuit 100 enters the negative current limit mode. The secondthreshold VTNL is indicative of a minimum negative current −ITNL of thenegative current limit mode. In response to the current through powertrain circuit 101 reaching the minimum negative current −ITNL, powerconverter circuit 100 exits the negative current limit mode and returnsto pulse width modulation mode.

The first threshold VTNU and the second threshold VTNL of hystereticcomparator circuit 302 are determined by the reference voltage VREFB andother characteristics of comparator circuit 302. The reference voltageVREFB may be programmably adjustable by a user or by other circuitry tovary the thresholds of hysteretic comparator circuit 302. Because twodifferent programmable reference voltages VREFA and VREFB are used todetermine the thresholds of comparator circuits 301 and 302,respectively, the negative current limit −ITNU can be programmed to be adifferent current value than the absloute value of the positive currentlimit ITPU. Alternatively, the negative current limit −ITNU can beprogrammed to be the absloute value of the positive current limit ITPU.

Further details of how power converter circuit 100 enters and exits thenegative current limit mode are now described. During the normaloperation of hysteretic comparison circuit 106, hysteretic comparatorcircuit 302 monitors the current sense signal CS to determine when anegative current through power train circuit 101 reaches or exceeds thenegative current limit −ITNU. The current through power train circuit101 is a negative current when the inductor current IL flows in theopposite direction of the arrow shown for IL in FIG. 1 from inductor 114through transistor 111 to V_(IN) or through transistor 112 to ground.Negative current may flow through power train 101, for example, if theload suddenly transitions from drawing a heavy load current to drawing alight load current from power converter 100. An increasing negativecurrent refers to the power train current falling farther below zero(i.e., a current flowing in inductor 114 toward node N1 increasing). Adecreasing negative current refers to the power train current risingcloser to zero (i.e., a current flowing in inductor 114 toward node N1decreasing).

The current sense signal CS decreasing to the first threshold VTNU ofhysteretic comparator circuit 302 indicates that a negative currentthrough power train circuit 101 has reached the negative current limit−ITNU. In response to the current sense signal CS decreasing to thefirst threshold VTNU of hysteretic comparator circuit 302, hystereticcomparator circuit 302 asserts its output drive signal HYSDR2 to a logichigh state, causing NOR gate circuit 303 to de-assert the CNTL signal toa logic low state, and causing power converter 100 to enter the negativecurrent limit mode. In response to signal CNTL being in a logic lowstate, gate circuit 103 prevents the values of the PWM signals frompropagating to the PWMDR signals. Thus, hysteretic comparison circuit106 prevents the PWM signals from controlling the conductive states ofswitching transistors 111-112 during the negative current limit mode.

In response to receiving a logic high state in drive signal HYSDR2,driver circuit 102 turns transistor 111 on if transistor 111 is off andturns transistor 112 off if transistor 112 is on. Driver circuit 102maintains the main switching transistor 111 on and maintains theauxiliary switching transistor 112 off during the negative current limitmode in response to the logic high state in drive signal HYSDR2. As aresult of transistor 111 being on and transistor 112 being off, thenegative current through inductor 114 decreases. By causing the negativecurrent through inductor 114 to decrease in the negative current limitmode, the current limit circuit prevents the negative current throughpower train 101 from substantially exceeding the negative current limit−ITNU. Although delay in the current limit circuit may allow thenegative current through power train circuit 101 to briefly exceed thenegative current limit −ITNU.

During the negative current limit mode of power converter 100,hysteretic comparator circuit 302 monitors the current sense signal CSto determine when the negative current through power train circuit 101has decreased to be equal to or less than the minimum negative current−ITNL of the negative current limit mode. The current sense signal CSincreasing to the second threshold VTNL of hysteretic comparator circuit302 indicates that the negative current through power train circuit 101has decreased to the minimum negative current −ITNL of the negativecurrent limit mode. In response to the current sense signal CSincreasing to the second threshold VTNL of hysteretic comparator circuit302, hysteretic comparator circuit 302 de-asserts its output drivesignal HYSDR2 to a logic low state, causing NOR gate circuit 303 toassert the CNTL signal to a logic high state, and causing powerconverter 100 to re-enter the pulse width modulation mode. When powerconverter 100 is in the negative current limit mode, the output signalHYSDR1 of hysteretic comparator circuit 301 is in a logic low state, andtherefore, the output signal CNTL of NOR gate circuit 303 is controlledby comparator circuit 302.

In response to the CNTL signal being in a logic high state, gate circuit103 passes the values of the PWM signals to signals PWMDR. In responseto driver circuit 102 receiving a logic low state in drive signalHYSDR2, driver circuit 102 controls the conductive states of transistors111 and 112 based on the PWMDR signals. Controller circuit 104 thencontrols the conductive states of transistors 111-112 again using thePWM signals during pulse width modulation mode. Controller circuit 104and driver circuit 102 control the current through power train 101 inresponse to the current drawn by the load as indicated by the outputvoltage V_(OUT) during pulse width modulation mode as described above.

FIG. 4B is a timing diagram that illustrates an example of the currentthrough power train circuit 101 as power converter circuit 100 entersand exits the negative current limit mode, according to an embodiment.In the example of FIG. 4B, the negative current through power traincircuit 101 (shown on the y axis) increases until the negative currentreaches the negative current limit −ITNU. In response to the negativecurrent through the power train 101 reaching −ITNU, power convertercircuit 100 enters the negative current limit mode, and the negativecurrent through the power train 101 decreases as described above. Thenegative current through power train 101 then decreases to the minimumnegative current −ITNL of the negative current limit mode. In responseto the negative current through power train 101 reaching −ITNL, powerconverter circuit 100 enters the pulse width modulation mode again. Thecurrent through the power train circuit 101 varies in pulse widthmodulation mode depending on the current drawn by the load. In theexample of FIG. 4B, the negative current through power train circuit 101increases during each pulse width modulation mode until the negativecurrent limit −ITNU is reached. As specific examples that are notintended to be limiting, −ITNL and −ITNU may be −40 amps and −60 amps,respectively.

FIG. 5 is a flow chart showing operations that may be performed todetermine when power converter circuit 100 enters and exits the positivecurrent limit mode, according to an embodiment. As disclosed above,power converter circuit 100 continuously monitors the current throughpower train circuit 101 using current sensor circuit 105 and hystereticcomparison circuit 106. In operation 501, hysteretic comparison circuit106 determines that the current through power train circuit 101 hasreached the positive current limit ITPU, for example, as described withrespect to FIG. 3. In operation 502, hysteretic comparison circuit 106controls the conductive states of switching transistors 111-112 in thepositive current limit mode to reduce the current through power traincircuit 101, as described above. In operation 503, hysteretic comparisoncircuit 106 determines that the current through power train circuit 101has reached the positive minimum current ITPL, as described above. Inoperation 504, hysteretic comparison circuit 106 allows controllercircuit 104 to control the conductive states of switching transistors111-112 in pulse width modulation mode using the PWM signals, asdescribed above. In operation 504, power converter circuit 100 exits thepositive current limit mode. Power converter circuit 100 maysubsequently return to operation 501 if the current in power train 101reaches ITPU again.

FIG. 6 is a flow chart showing operations that may be performed todetermine when power converter circuit 100 enters and exits the negativecurrent limit mode, according to an embodiment. In operation 601,hysteretic comparison circuit 106 determines that a negative current inpower train circuit 101 has reached the negative current limit −ITNU,for example, as described with respect to FIG. 3. In operation 602,hysteretic comparison circuit 106 controls the conductive states ofswitching transistors 111-112 in the negative current limit mode todecrease the negative current in power train circuit 101, as describedabove. In operation 603, hysteretic comparison circuit 106 determinesthat the current in power train circuit 101 has reached the minimumnegative current −ITNL, as described above. In operation 604, hystereticcomparison circuit 106 allows controller circuit 104 to control theconductive states of switching transistors 111-112 in pulse widthmodulation mode using the PWM signals, as described above. In operation604, power converter circuit 100 exits the negative current limit mode.Power converter circuit 100 may subsequently return to operation 601 ifthe current in power train 101 reaches −ITNU again.

According to another embodiment, two power converter circuits 100 arecoupled in parallel to provide output current to a single load at anoutput node. In this embodiment, a first one of the power convertercircuits is set to regulate the voltage at the output node to a firstoutput voltage, and the second power converter circuit regulates thevoltage at the output node to a second output voltage that is greaterthan the first output voltage. The first and second power convertercircuits operate independently of each other. The first and second powerconverter circuits independently transition into and out of the PWM,positive current limit, and negative current limit modes.

According to yet another embodiment, a power converter circuit includestwo power train circuits 101, two driver circuits 102, and a single oneof each of the circuits 103-106 shown in FIG. 1. Each driver circuit 102controls the current in one of the two power train circuits 101. In thisembodiment, driver circuits 102 control power train circuits 101 in PWMmode based on the PWM signals generated by the single controller circuit104. Driver circuits 102 control the currents in power train circuits101 in the positive and negative current limit modes in response to theoutput drive signals HYSDR of the single hysteretic comparison circuit106, as described above.

According to still another embodiment, the techniques disclosed hereinwith respect to measuring and limiting a positive current in a powertrain circuit can be employed in a power train circuit in whichswitching transistor 112 is replaced with a diode. Current in the diodeonly flows in the positive direction from ground to inductor 114.Current sensor circuit 105 and hysteretic comparison circuit 106 limitthe outgoing positive current through the power train circuit to theload as disclosed herein.

The methods and apparatuses disclosed herein may be incorporated intoany suitable electronic device or system of electronic devices. Themethods and apparatuses may be used to power numerous types ofintegrated circuits, such as programmable array logic (PAL),programmable logic arrays (PLAs), field programmable logic arrays(FPLAs), electrically programmable logic devices (EPLDs), electricallyerasable programmable logic devices (EEPLDs), logic cell arrays (LCAs),field programmable gate arrays (FPGAs), application specific standardproducts (ASSPs), application specific integrated circuits (ASICs),digital signal processors (DSPs), microprocessors, and graphicsprocessing units (GPUs).

The power converter circuits disclosed herein may be part of a dataprocessing system that includes one or more of the following components;a processor; memory; input/output circuitry; and peripheral devices. Thepower converter circuits can be used in a wide variety of applications,such as computer networking, data networking, instrumentation, videoprocessing, digital signal processing, or any other application.

Although the method operations were described in a specific order, itshould be understood that other operations may be performed in betweendescribed operations, described operations may be adjusted so that theyoccur at different times or in a different order, or describedoperations may be distributed in a system that allows the occurrence ofthe processing operations at various intervals associated with theprocessing.

The foregoing description of the exemplary embodiments of the presentinvention is not intended to be exhaustive or to limit the presentinvention to the examples disclosed herein. In some instances, featuresof the present invention can be employed without a corresponding use ofother features as set forth. Many modifications, substitutions, andvariations are possible in light of the above teachings, withoutdeparting from the scope of the present invention.

What is claimed is:
 1. A power converter circuit comprising: a currentsensor circuit that generates an indication of a current through a powertrain circuit, wherein the power converter circuit controls the currentthrough the power train circuit; and a hysteretic comparison circuitthat compares the indication of the current through the power traincircuit to a negative current limit, wherein the power converter circuitcauses a negative current in the power train circuit that is flowingaway from an output node of the power train circuit to decrease inresponse to an indication generated by the hysteretic comparison circuitthat the negative current in the power train circuit has reached thenegative current limit.
 2. The power converter circuit of claim 1further comprising: a controller circuit that generates a pulse widthmodulation signal in response to a signal from the power train circuit,wherein the power converter circuit controls the current through thepower train circuit in response to the pulse width modulation signalduring a pulse width modulation mode; and a gate circuit that preventsthe power converter circuit from controlling the current through thepower train circuit using the pulse width modulation signal in responseto the indication generated by the hysteretic comparison circuit thatthe negative current in the power train circuit has reached the negativecurrent limit.
 3. The power converter circuit of claim 1, wherein thecurrent sensor circuit continuously monitors the current through thepower train circuit to generate the indication of the current throughthe power train circuit during an on time of a first switchingtransistor in the power train circuit and during an on time of a secondswitching transistor in the power train circuit.
 4. The power convertercircuit of claim 1, wherein the hysteretic comparison circuit comprises:a first hysteretic comparator circuit that generates a first drivesignal by comparing first and second thresholds to a current sensesignal, wherein the current sensor circuit generates the current sensesignal as the indication of the current through the power train circuit,and wherein the power converter circuit controls the current through thepower train circuit in response to the first drive signal during anegative current limit mode.
 5. The power converter circuit of claim 4,wherein the first threshold is indicative of the negative current limitof the negative current in the power train circuit, wherein the secondthreshold is indicative of a minimum negative current of the negativecurrent limit mode, wherein the power converter circuit enters thenegative current limit mode in response to the negative current in thepower train circuit reaching the negative current limit, wherein thepower converter circuit causes a switching transistor in the power traincircuit to couple an inductor to an input node at an input voltageduring the negative current limit mode, and wherein the power convertercircuit exits the negative current limit mode in response to thenegative current in the power train circuit reaching the minimumnegative current of the negative current limit mode.
 6. The powerconverter circuit of claim 4, wherein the hysteretic comparison circuitfurther comprises: a second hysteretic comparator circuit that generatesa second drive signal by comparing third and fourth thresholds to thecurrent sense signal, wherein the power converter circuit controls thecurrent through the power train circuit in response to the second drivesignal during a positive current limit mode.
 7. The power convertercircuit of claim 6, wherein the third threshold is indicative of apositive current limit of the current through the power train circuit,wherein the fourth threshold is indicative of a minimum current of thepositive current limit mode, wherein the power converter circuit entersthe positive current limit mode in response to the current through thepower train circuit reaching the positive current limit, wherein thepower converter circuit causes a switching transistor in the power traincircuit to couple an inductor in the power train circuit to a groundnode during the positive current limit mode, and wherein the powerconverter circuit exits the positive current limit mode in response tothe current through the power train circuit reaching the minimum currentof the positive current limit mode.
 8. The power converter circuit ofclaim 7, further comprising: a controller circuit that generates a pulsewidth modulation signal in response to a signal from the power traincircuit to control the current through the power train circuit and toregulate an output voltage at the output node during a pulse widthmodulation mode, wherein the hysteretic comparison circuit furthercomprises a first logic gate circuit that performs a logic function onthe first and second drive signals to generate a control signal, whereinthe first logic gate circuit de-asserts the control signal to indicatethat the current through the power train circuit has reached thenegative current limit or the positive current limit; and a second logicgate circuit that prevents the power converter circuit from controllingthe current through the power train circuit using the pulse widthmodulation signal in response to the control signal being de-asserted.9. The power converter circuit of claim 1, wherein the power traincircuit comprises first and second switching transistors, wherein thepower converter circuit controls current through an inductor bycontrolling conductive states of the first and second switchingtransistors, wherein the first switching transistor is coupled betweenan input node at an input voltage and the inductor, and wherein thesecond switching transistor is coupled between the inductor and a groundnode.
 10. A power converter circuit comprising: a power train circuitcomprising a first switching transistor, wherein the power convertercircuit turns the first switching transistor on and off in response to apulse width modulation signal in a pulse width modulation mode tocontrol a current in the power train circuit; a hysteretic comparisoncircuit that causes the power converter circuit to control the currentin the power train circuit in a first current limit mode in response tothe current in the power train circuit reaching a first current limit;and a gate circuit that prevents the power converter circuit fromcontrolling the current in the power train circuit using the pulse widthmodulation signal during the first current limit mode in response to thehysteretic comparison circuit indicating that the current in the powertrain circuit has reached the first current limit.
 11. The powerconverter circuit of claim 10, wherein the hysteretic comparison circuitcauses the power converter circuit to control the current in the powertrain circuit in a second current limit mode in response to the currentin the power train circuit reaching a positive current limit, whereinthe first current limit is a negative current limit, and wherein thegate circuit prevents the power converter circuit from controlling thecurrent in the power train circuit using the pulse width modulationsignal during the second current limit mode in response to thehysteretic comparison circuit indicating that the current in the powertrain circuit has reached the positive current limit.
 12. The powerconverter circuit of claim 10 further comprising: a current sensorcircuit that monitors the current in the power train circuit to generatea signal indicative of the current in the power train circuit during anon time of the first switching transistor and during an on time of asecond switching transistor in the power train circuit, wherein thesignal indicative of the current in the power train circuit is providedto the hysteretic comparison circuit.
 13. The power converter circuit ofclaim 12, wherein the first current limit is a negative current limit,wherein the hysteretic comparison circuit compares the signal indicativeof the current in the power train circuit to a first thresholdindicative of the negative current limit, wherein the power convertercircuit causes a negative current in the power train circuit that isflowing away from an output node of the power train circuit to decreasein the first current limit mode in response to the hysteretic comparisoncircuit indicating that the negative current in the power train circuithas reached the negative current limit.
 14. The power converter circuitof claim 13, wherein the hysteretic comparison circuit compares thesignal indicative of the current in the power train circuit to a secondthreshold that is indicative of a minimum negative current of the firstcurrent limit mode, and wherein the power converter circuit exits thefirst current limit mode and returns to the pulse width modulation modein response to the negative current in the power train circuit reachingthe minimum negative current of the first current limit mode.
 15. Thepower converter circuit of claim 13, wherein the hysteretic comparisoncircuit compares the signal indicative of the current in the power traincircuit to a second threshold that is indicative of a second currentlimit, wherein the power converter circuit causes the current in thepower train circuit to decrease in a second current limit mode inresponse to the hysteretic comparison circuit indicating that a positivecurrent in the power train circuit that is flowing toward the outputnode of the power train circuit has reached the second current limit.16. The power converter circuit of claim 15, wherein the hystereticcomparison circuit compares the signal indicative of the current in thepower train circuit to a third threshold indicative of a positiveminimum current of the second current limit mode, and wherein the powerconverter circuit exits the second current limit mode and returns to thepulse width modulation mode in response to the positive current in thepower train circuit reaching the positive minimum current of the secondcurrent limit mode.
 17. A method comprising: generating an indicationthat a positive current in a power train circuit has reached a positivecurrent limit using a hysteretic comparison circuit; decreasing thepositive current in the power train circuit in a positive current limitmode using a driver circuit in response to the indication that thepositive current in the power train circuit has reached the positivecurrent limit; generating an indication that a negative current in thepower train circuit has reached a negative current limit using thehysteretic comparison circuit; and decreasing the negative current inthe power train circuit in a negative current limit mode using thedriver circuit in response to the indication that the negative currentin the power train circuit has reached the negative current limit,wherein the driver circuit and the hysteretic comparison circuit arepart of a power converter circuit.
 18. The method of claim 17 furthercomprising: generating a signal indicative of the positive current andthe negative current in the power train circuit using a current sensorcircuit during an on time of a first switching transistor in the powertrain circuit and during an on time of a second switching transistor inthe power train circuit, wherein the hysteretic comparison circuitgenerates the indication that the positive current in the power traincircuit has reached the positive current limit and the indication thatthe negative current in the power train circuit has reached the negativecurrent limit in response to the signal indicative of the positivecurrent and the negative current in the power train circuit.
 19. Themethod of claim 17 further comprising: exiting the positive currentlimit mode in response to the positive current in the power traincircuit reaching a positive minimum current of the positive currentlimit mode; and exiting the negative current limit mode in response tothe negative current in the power train circuit reaching a minimumnegative current of the negative current limit mode.
 20. The method ofclaim 17 further comprising: generating a pulse width modulation signalusing a controller circuit in response to a signal from the power traincircuit to control a current in the power train circuit in a pulse widthmodulation mode; and preventing the controller circuit from controllingthe current in the power train circuit in the pulse width modulationmode in response to the indication that the positive current in thepower train circuit has reached the positive current limit or inresponse to the indication that the negative current in the power traincircuit has reached the negative current limit.